The present invention relates to a semiconductor device formed in a semi-insulative substrate.
A pellet having an FET (field effect transistor) formed in, for example, a GaAs substrate is generally sealed in a casing as shown in FIG. 1. As seen from the drawing, a pellet 11 comprising a source electrode 15, a drain electrode 16 and a gate electrode 17 is mounted on a mount portion 12a of a source lead 12. Also, a drain lead 13 and a gate lead 14 are arranged apart from the mount portion 12a in a direction perpendicular to the extending direction of the source lead 12. Further, bonding wires 18, 19, 20 are provided to connect the source electrode 15, drain electrode 16 and gate electrode 17 to the source lead 12, drain lead 13 and gate lead 14, respectively. It is seen that the pellet 11, mount portion 12a and the end portions of the source lead 12, drain lead 13, gate lead 14 are sealed in the casing 21. The particular construction is thought optimum for shortening and widening the source lead 12 and for shortening the bonding wire 18 connecting the source electrode 15 of the pellet 11 to the source lead 12.
The particular sealing shown in FIG. 1 makes it possible to diminish the inductance Ls of the source lead 12. It is also possible to diminish the capacitance Cgd between the gate lead 14 and the drain lead 13 because the source lead 12 is interposed between the gate lead 14 and the drain lead 13. What should be noted is that the diminished inductance Ls and capacitance Cgd permit increasing the maximum available gain MAG of the FET. Specifically, the maximum effective gain MAG of the FET is represented as follows: EQU MAG=(f.sub.T /f).sup.2 /[4 gds(Rg+Ri+Rs+.pi.f.sub.T LS)+4.pi.f.sub.T Cgd(2Rg+Ri+Rs+2.pi.f.sub.T LS)]
where, "f.sub.T " denotes the cut-off frequency, "f" the operating frequency, "gds" the source-drain conductance, "Rg" the gate resistance, "Ri" the resistance of the channel right under the gate, and "Rs" the source resistance.
As apparent from the formula given above, the maximum available gain MAG is increased, if the source lead inductance Ls and/or the gate-drain capacitance Cgd are diminished.
FIG. 2 is a cross sectional view showing the construction of the pellet 11. It is seen that an N.sup.+ source region 23 and an N.sup.+ drain region 24 are formed in a semi-insulative GaAs substrate 22, with a channel region 25 being formed between the source and drain regions 23 and 24. Also, a source electrode 26, a drain electrode 27 and a gate electrode 28 are formed on the source region 23, drain region 24 and channel region 25, respectively. Further, a back electrode 29 is formed on the back surface of the substrate 22. The symbols I.sub.D and I.sub.EX shown in FIG. 2 denote the drain current (operating current) and excess leak current, respectively. To facilitate the description, the flow direction of current is shown equal to the flow direction of electrons. It should be noted that a shaded region 30 denotes a depletion layer extending downward from the gate electrode 28.
When the pellet 11 of the construction shown in FIG. 2 is mounted as shown in FIG. 1, the drain current I.sub.D is vibrated upon application of a DC bias between the source and drain regions 23 and 24. Originally, the drain current I.sub.D alone acts as the operating current of the FET. However, the excess leak current I.sub.EX flowing through the semi-insulative substrate 22 is thought to bring about vibration of the drain current I.sub.D because the excess leak current I.sub.EX contains AC components of about 10 to 100 Hz. It has been confirmed that generation and extinction of electrons take place within the semi-insulative GaAs substrate, giving rise to the AC components contained in the excess leak current I.sub.EX.
Since the potential of the source region 23 is higher than that of the drain region 24, the electrons E generated within the semi-insulative GaAs substrate flow as the excess leak current I.sub.EX into the drain region 24 through the depletion layer 31 formed in the lower portion of the FET operating region, as shown in FIG. 3. Flow of the electrons E through the depletion layer 31 causes a change in the width of the depletion layer, leading to a change in the width of the channel region. The change in the width of the channel region is thought to modulate the drain current I.sub.D, leading to vibration of the current flowing out of the drain electrode 27. Incidentally, vibration of current within a semi-insulative substrate is described in "Applied Physics Letter, 41 (10), Nov. 15, 1982 P. 989" and "1985 IEEE GaAs IC Symposium `Low Frequency Oscillation in GaAs IC`s`".
Vibration of the drain current I.sub.D brings about vibration of the high frequency gain Gps, leading to vibration of the total gain of the equipment having the FET element included in its electric circuit. When it comes to, for example, a TV tuner having the FET element incorporated therein, the TV screen is caused to flicker.